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Simulated Annealing for VLSI Design by D. F. Wong, H. W. Leong, Chung Laung Liu


Simulated Annealing for VLSI Design by D. F. Wong, H. W. Leong, Chung Laung Liu

This monograph represents a summary of our work in the last two years in applying the method of simulated annealing to the solution of problems that arise in the physical design of VLSI circuits. Our study is experimental in nature, in that we are con- cerned with issues such as solution representations, neighborhood structures, cost functions, approximation schemes, and so on, in order to obtain good design results in a reasonable amount of com- putation time. We hope that our experiences with the techniques we employed, some of which indeed bear certain similarities for different problems, could be useful as hints and guides for other researchers in applying the method to the solution of other prob- lems. Work reported in this monograph was partially supported by the National Science Foundation under grant MIP 87-03273, by the Semiconductor Research Corporation under contract 87-DP- 109, by a grant from the General Electric Company, and by a grant from the Sandia Laboratories.


`Individuals interested in design automation and, in particular, VLSI design will find this monograph a useful source of information on the application of the simulated annealing method.
Zentralblatt fur Mathematik, 699 (1991)

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Book Info

Publication date

31st March 1988


D. F. Wong, H. W. Leong, Chung Laung Liu

More books by D. F. Wong, H. W. Leong, Chung Laung Liu
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Kluwer Academic Publishers


202 pages


Functional analysis & transforms



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